*** See Miscellaneous for wearable language translation system
New items (01-14-2001) are in BLUE
SONALYSTS, INC.
215 Parkway North, P.O. Box 280
Waterford, CT 06385 Phone:
PI:
Topic#: (401) 849-0400
Michael W. Phelps
NAVY 00-052 Title: Application of Virtual Large Display Video Goggles to Submarine Imaging Systems Abstract: Sonalysts, Inc. proposes leveraging our Team's extensive research and development background with state-of-the-art visual technologies to introduce goggles displaying a large field of view video scene from the periscope imaging sensors. A number of benefits are offered to the imaging system operator and his supervisor, including filling the operator's field of view and reducing peripheral distractions, thereby creating a sense of "immersion" into the current scene; and enabling the supervisor to be mobile while viewing what the operator sees. Key Phase I objectives include: defining the operational and technical requirements that will be used to assess available technology and evaluate candidate goggles, demonstrating the video scene with prototype goggles, and developing the architecture for integration of goggles with the submarine imaging system hardware and software. Our focus will ensure that submarine fleet requirements and issues are addressed and weighed in the investigation of the most appropriate commercial off-the- shelf (COTS) components. We will ensure interoperability between all components and explore the commercial applications to broaden the opportunities of this topic area. Our proposed approach will advance the state-of-the-art applications for the submarine fleet and bring increased performance opportunities for the imaging operator and his supervisor. An immersive environment that allows mobility and flexibility will be the effect of the integration of COTS goggle technology. Commercial opportunities for goggles include remote surveillance and security monitoring uses, medical and surgical procedures, and machinery diagnostics and inspections.
MTL SYSTEMS, INC. 3481 Dayton-Xenia Rd. Beavercreek, OH 45432
Phone: PI: Topic#: (937) 426-3111 Larry Guthrie AF 00-107
Title: Automated Multi-Level Security Digital Information Transfer Using Watermarking Technologies
Abstract: MTL Systems, Inc., Dr. Jiri Fridrich, and Sterling Software propose a robust digital watermarking technique that will enable near real time automatic transfer of complex data types, such as imagery, among multi-level, secure networks. The security level is embedded in a robust invisible manner in the image multiple times rather than attached to it. This makes the embedding and extraction process independent of the image format. Both the watermark embedding and extraction are protected by a secret key. We propose to embed the security level using spread-spectrum watermarking techniques in the spatial and the transform domain. The security level can be extracted after common image processing operations. To make the extraction possible for images that underwent geometrical transformations, a synchronization pattern will be embedded in the image in addition to the watermark. Given the right secret key, the watermark can be removed, the image processed, and a new watermark can be embedded. Our Phase I Objectives are to (1) analytically and experimentally assess feasibility, (2) demonstrate a working prototype, (3) produce a preliminary design for Phase II and (4) assess commercial product potential. Meeting these objectives will ensure both a successful Phase II effort and a focused approach to commercialization.
3DVIS TECHNOLOGIES, INC.
717 Mirador Rd
Vestal, NY 13850 Phone:
PI:
Topic#: (607) 748-8872
Peter Sulatycke
AF 00-126 Title: FASTCP: A Low Latency TCP/IP Software for Accelerating Commodity LANs Abstract: With the steadily dropping costs of computing and networking hardware, local area networks (LANs) have proliferated widely. Unfortunately, the software delays of the standard TCP/IP networking protocol suite (and its associated operating system services) grossly underutilizes the full performance potential of modern networks. We propose the development of an alternative version of TCP that speeds up the performance of Ethernet based LANs by as much as 8 to 10 times while maintaining full programming compliance with standard TCP. This allows applications to run without any change, but allows network applications within the LAN to run significantly faster. The basic product can also be extended to provide similar benefits to LANs that use modern technologies such as Myrinet, Fibre Channel, Gigabit Ethernet and ATM. Such a product is obviously dual-use in nature and can significantly expand current markets and also create new markets in the cluster computing and data server arena. This product thus has the potential of enhancing the competitive advantage of the nation.
CFD RESEARCH CORP.
215 Wynn Drive, 5th floor
Huntsville, AL 35805 Phone:
PI:
Topic#: (256) 726-4800
Phillip Stout
DARPA 00-024 Title: CAD Tool for Terahertz Device Development Abstract: The overall objective of this effort is to develop a commercial quality, validated computer aided design (CAD) tool to aid in the development of THz quantum based semiconductor devices. THz device design must account for quantum effects such as quantum resonant modes, quantum mode mixing, tunneling, intersubband transitions, side wall scattering, and surface recombination. Currently, there are no CAD tools available that incorporate all the proper physics for designing THz quantum devices. The proposed quantum CAD tool will be a device simulator with the ability to investigate the operation of and generate reduced models (S-parameters) for quantum based, electronic and photonic THz sources and detectors such as quantum cascade lasers, superlattices, and multiple quantum wells. In phase I an existing quantum simulator, NEMO, will be coupled to drift-diffusion and/or hydrodynamic models to enable multi-scale studies of semiconductor devices. Physics for optical pumping effects will be added to the AC analysis to allow the study of laser illuminated devices such as a THz receiver. The quantum device simulator linked to classical models will be demonstrated and verified on several different Quantum devices using published experimental results. Finally, the tool will be integrated into CFDRC's commercial CAD environment. The integration will leverage existing commercial physics models, numerical solver, database, and GUI library technologies at CFDRC.
SADDLEBACK AEROSPACE
10523 Humbolt Street
Los Alamitos, CA 90720 Phone:
PI:
Topic#: (562) 598-3700
Geoffrey O. Campbell
AF 00-040 Title: Boiling Enhanced Micro-Channel Heat Sink for Electronic Cooling Abstract: As semiconductor devices are driven towards higher powers and faster speeds, they require more capable thermal management technologies. This has led to the use of high performance microchannel cooling, but further improvements in heat transfer performance are sought to: 1) improve temperature stability in the coolers, and 2) increase the heat flux limits of microchannels. Boiling is a potential way to limit the temperature in the coolers, reduce coolant usage, and increase internal heat transfer coefficients. However, only a handful of studies have been performed on 2-phase microchannel flows. The Phase I effort is designed to characterize the fluid and heat transfer physics of 2-phase flows in microchannel systems. The proposed work involves an extensive set of flow visualization experiments in silicon microchannels. The experimental work is complemented by analytic interpretation of the results, generating heat transfer and pressure drop correlations for 2-phase flows in micro-ducts. This will provide the needed understanding to support development of design tools for the generation of cooling systems for laser diodes and electronics. This understanding will be demonstrated during the Phase I program through the fabrication of a microchannel cooler optimized for 2-phase flow.
| REVEO, INC. 8 Skyline Dr. Hawthorne, NY 10532 |
|
| Phone: PI: Topic#: |
(914) 345-9555 Bunsen Fan BMDO 96-011 |
| Title: Chiral Film Technology for Ultrahigh-Capacity & Ultrafast Retrieval Optical Storage | |
| Abstract: Reveo invented a novel optical storage technology that increases the storage capacity and data transfer rate by an order of 1,000 over that of the present-day CD-ROMs, while maintaining 'backward' compatibility. The technology uses the unique optical properties of chiral films to achieve wavelength division and polarization discrimination multiplexing of read channel signals. The storage medium, which can also be card or tape formats, consists of 1,000 or so information-carrying layers coated with a patterned chiral thin film. The chiral film is obtained with innovative vacuum deposition techniques. As an example, a 10-mm thick disc of diameter 120mm has a storage capacity of 650GBytes, if an infrared ("lambda" = 0.78um) laser is used for data retrieval. This corresponds to an equivalent volumetric density of 7GByte/cm(3). With parallel readout, a data transfer rate greater than 150GByte/s is possible. More importantly, the proposed optical storage technology can utilize advances in short-wavelength diode lasers to increase the storage capacity even further. Furthermore, the 'backward' compatibility provides a natural and viable migrating path for rapid introduction to the market. | |
NONVOLATILE ELECTRONICS, INC. |
|
| Phone: PI: Topic#: |
(612) 829-9217 Robert A. Sinclair AF 98-058 |
| Title: | Mechanically Hard, Event Recorder with Nonvolatile Memory |
| Abstract: | A data recording system will be designed that will be smaller than the recorders presently available and contain high speed nonvolatile memory to guard against data loss when power fails. Various nonvolatile memory technologies will be investigated including a new memory technology called MRAM (magnetoresistive random access memory) which has all the characteristics required including fast write times, no wear out mechanisms, no loss of data when the battery fails, high shock tolerance, wide temperature range and low power. A 32k x 8 MRAM chip using NVEs proprietary GMR material which is currently being developed for Eglin AFB will be evaluated to determine its suitability to the needs of this program. Commercial high density packaging techniques will be evaluatedwhich can survive 100k g and samples of the selected technology will be tested with NVE's in-house High G Tester (HGT). Experience gained during a Phase I program for Eglin AFB will be used as a basis for this investigation. A data recorder, using high density nonvolatile memory components, high shock MCM technology, and a new miniature lithium battery technology will be designed to fit within a volume of 1 cubic inch and survive shocks over 100,000 g's. |
SYSTEM EXCELERATOR, INC. |
|
| Phone: PI: Topic#: |
(407) 290-6148 Martin Tanenhaus AF 98-058 |
| Title: | G Hardened Miniaturized Event Recorder with Nonvolatile Memory |
| Abstract: | System Excelerator Inc. (SEI) proposes to implement the first phase of a two phase development effort to create a G-hardened miniaturized event recorder. In this first phase SEI will develop a design for a recorder that will allow sensors to be triggered by an event, manually or periodically, and store the data in nonvolatile memory. The proposed architecture for transient data capture is capable of capturing and processing up to eight channels of sensor data simultaneously from one or two analog to digital converters, analyzing and summarizing the captured data, and storing the data in flash memory until needed. The modular nature of the design allows for different types of single or multi-axis sensor modulars to be used with different g sensitivity thresholds. To implement data recovery, a standard serial connection and command set used to connect the recorder to a PC. |
INTELLIGENT AUTOMATION, INC. |
|
| Phone: PI: Topic#: |
(301) 590-3155 JIANHONG CAI AF 98-122 |
| Title: | AN OPTOELECTRONIC THYRISTOR BASED ANALOG TO DIGITAL CONVERTER |
| Abstract: | A unique thyristor laser implements a high performance Analog to Digital Converter (ADC) in a monolithic FET GaAs integrated circuit. In the curent high speed FLASH ADC, the comparator circuit performs in the sampling on the input analog signal by comparing it to a voltage reference tree and the outputs are converted to binary form via a decimal to binary (DTB) algorithm stored in a ROM. To achieve substantial increases in ADC accuracy, speed and circuit density, we propose a comparator based on an optoelectronic thyristor which is electrically switched and provides laser ouput as a VCSEL in the on state. We introduce an elegant new architecture to implement the ADC function which merges the roles of the quantization, the DTB conversion and the O/E conversion within a simple integrated circuit. One thyristor and one Differential amplifier are required per binary digit. This new approach reduces the number of devices required for a 12 bit ADC from 100,000 to 70 and reduces the ADC delay from 50ns to 0.5ns. The power is correspondingly reduced and the output is a digital optical signal in serial or parallel format. The voltage resolution is in the 5mV range limited only by the dark current noise in the switch. This approach provides a quantum leap in an N bit ADC speed because the output is obtained optically in the time that it takes the analog signal to ripple through N stages at 40ps/stage. This technique promises to revolutionize the art of ADC and to provide the basis for very high speed image transfer for the future all digital network. In addition to this novel conversion we also provide the integrated technology to realize the VCSEL thyristor, the FET amplifier and CCD sensor simultaneously. |
SYSTEMS & PROCESSES ENGINEERING
CORP. |
|
| Phone: PI: Topic#: |
(512) 306-1100 JOE PRIEST OSD 98-008 |
| Title: | HIGH SPEED HIGH DENSITY SOLID STATE RECORDER |
| Abstract: | Systems & Processing Engineering Corporation proposes to develop a High Speed High Density Solid State Recorder to meet the data rate and storage requirements of the next generation reconnaissance sensors. The recorder will have a high data throughput, low bit error rate, high density storage and be capable of operation in an airborne environment. The design will exploit the use of memory technologies such as micro ball grid array, flip chip technology, state-of the-art Synchronous Dynamic Random Access Memory, Electrically Erasable Programmable Read-Only Memory. Other technologies including Application Specific Integrated Circuit and Multi-Chip Module technologies will be used to meet stringent volume and performance requirements and increase reliability.The baseline configuration will be capable of storing 1500 Gb of data with a sustained data rate of greater than 10 Gbps and a maximum BER of 1E-14 in a volume of less than 1.5 cubic feet. The modular design approach allows for customization of data inputs, outputs and memory configurations as well as enhanced reliability and maintainability. Power management techniques will be incorporated to limit power consumption to less than 100W. |
ANACAPA SCIENCES, INC. |
|
| Phone: PI: Topic#: |
(805) 966-6157 Alan Spiker AF 99-102 |
| Title: | Area of Interest & Image Warping Presentation of Large Schematics on Small Computer Displays |
| Abstract: | The objective of the proposed effort is to determine the feasibility of squeezing a large schematic or diagram image onto a small physical display using a high-resolution area-of-interest in conjunction with warping of the remaining imagery. The resulting, hybrid image can then be viewed by maintenance personnel as they perform their tasks using portable computers. The specification of the area-of-interest size and shape, the algorithms used to warp the background, and the pointing methods used to interact with the images are collectively referred to as the EyeWarp system. This approach to economizing a large image is supported by our knowledge of how we view our visual world and our reliance on awareness of the entire scene. Analogously, the presence of the total image is important in maintaining awareness of what we are looking at, and where we are located in a large complex computer-based schematic or diagram. In Phase I, we will survey the range of maintenance schematics and diagrams and candidate portable displays, evaluate the feasibility of the EyeWarp concept, and perform a series of user experiments to identify parameters that optimize the usability of the concept. Evaluation of key area-of-interest and warping parameters will be accomplished using computer graphics and image processing software with a desktop monitor, as will the simulation of pointing and warping. Deliverables will include a final technical report and demonstration EyeWarp software. |
| QUALITY RESEARCH, INC.
4901-D Corporate Drive Huntsville, AL 35805 |
|
| Phone: PI: Topic#: |
(256) 864-8222 Lawrence A. Tubbs BMDO 99-010 |
| Title: | A 3D Pointer for Volumetric and Other Virtual 3D Environments |
| Abstract: | This project will produce a 3D Pointer for "fishbowl 3D" and volumetric 3D displays. Virtual 3D displays using 2D devices have become standard tools for simulations. These displays can provide virtual environments where users may train for complex tasks. Alternatively, developers have made significant progress toward realistic 3D displays using several volumetric display techniques. Both fishbowl and volumetric displays have great potential for application to command and control (C2) functions. C2 application of these technologies awaits the development of a simple, "drag-and-drop" mechanism usable by the average business manager. Digital appendages and 3D controllers have provided tools for expert computer users. These devices are either: expensive and cumbersome to the user (digital gloves and head-mounted displays); or require complex motions and mode changes (3D mice and 3D joysticks). What is lacking is a technology for pointing, selecting, and moving objects in 3D environments, taking advantage of the human instinct to select by pointing and the current generation's expertise in "drag-and-drop" methods. Integrating commercial 3D technologies and developing software drivers, the project will produce a pointing device for 3D targeted to real-world managers. The device will be suited for object control in the fishbowl and volumetric 3D displays. |
STI |
|
| Phone: PI: Topic#: |
(301) 881-2111 Jim Farmer NAVY 99-153 |
| Title: | Sneak Circuit Analysis For Software |
| Abstract: | Large scale integrated systems are often plagued by sneak conditions because they are comprised of several different components that are designed independently by different groups. Design reuse, cross-pollination of requirements, insufficient system component modeling, continual requirements changes and inherent design process weaknesses make sneak paths more likely to occur and more difficult to detect in these complex systems. Software sneak paths in particular are typically not caught by evaluation or test, resulting in operational errors and outright failures in fielded systems. Sneak Circuit Analysis (SCA) is a proven process that eliminates unwanted paths in electronic systems and has been successfully applied to Software Sneak Path Analysis (SSPA). STi proposes to study present design process and available case reports of integrated combat and warfare systems to identify root causes of software sneak paths. Based on our research, coupled with our extensive SCA experience, we will: (1) recommend changes to design procedures and processes; (2) determine whether analysis techniques can be developed around existing models; (3) identify minimum system modeling requirements; and (4) define requirements for software tools to be developed and tested in Phase II that have potential to eliminate the hidden effects and enable designers to focus on performance. |
SIERRA MONOLITHICS, INC. |
|
| Phone: PI: Topic#: |
(310) 379-2005 David Rowe DARPA 97-060 |
| Title: | High Speed Analog to Digital Converter Using SiGe Technology |
| Abstract: | Sierra Monolithics, Inc. (SMI) proposes to develop a 16-bit, 2 GS/s A/D Converter using a novel Delta-Sigma architecture to achieve the bit resolution and incorporating IBM's Silicon Germanium (SiGe) BiCMOS process for the requisite speed. Commercial A/D converters on silicon or GaAs do not simultaneously provide GHz sampling rate and high 16-bit resolution. In order to satisfy both of these performance criteria for a 100 MHz input signal bandwidth, the device technology has to be fast enough to reduce the sampling aperture jitter down to less than 50 fsec and the digitizing error to 15 ŠV. SMI proposes an A/D converter approach that will meet these requirements. The approach uses IBM's SiGe HBT technology for low jitter (5 fsec), high sample rate (2 GS/s) and a unique Delta-Sigma architecture for the digitizing accuracy. The novel Delta-Sigma architecture uses a second order noise shaping single loop, dynamic element matching for improved DAC accuracy, and linearity enhanced subtraction circuit with an embedded DAC to achieve 16-bit resolution. System design and device simulation for the A/D converter will be performed in Phase I while fabrication and test will be performed in Phase II. |